1. Field of the Invention
The invention relates to a digital phase-locked loop, and more particularly, to a digital phase-locked loop having a three-state phase frequency detector (PFD).
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional digital phase-locked loop. As shown in FIG. 1, the phase/frequency analog-to-digital converter (PFDC) 1 receives the digital signals of square waves I1 and I2 and detects the phase difference value (Δψ) between these two digital signals. The phase difference value is obtained as analog information, and the phase/frequency analog-to-digital converter 1 needs to convert the analog information into digital information for the filter 2. Since the phase difference value is obtained as analog information, the phase/frequency analog-to-digital converter 1 needs to be implemented with multiple bits, which may increase the cost and complexity of the circuit. Therefore, it is desired to provide a low-cost digital phase-locked loop.